1. Field of Invention
This invention relates to automated integrated circuit design data and, more specifically, to routing congestion removal during block placement, particularly for custom design.
2. Description of Related Art
A typical custom/analog design flow 100 is shown in FIG. 1 and starts with design entry 101; generally it is done through schematic entry or HDL representation. The design entry is done carefully to meet the design specification and is verified by simulation 103. When a design meets the required specification (“Yes”, 105) then its physical implementation starts which is known a physical design.
Physical design can be broadly categorized into following stages:
1. Layout Entry 107
2. Floorplanning 109
3. Routing
Layout Entry 107 is the first step of physical design which is a physical representation of a design. At the floorplanning stage 109, the design is partitioned into various blocks depending upon the net connectivity between the layout components. The blocks are optimally placed in the entire design space such that wire length and chip area are minimum. After the floor planning, the next step is routing which can be divided into two parts.
1. Global routing 111
2. Detailed routing 117
Global routing determines the routing paths and routability of the design, whereas the detailed routing does the actual routing of wires. After the detailed routing, the flow continues at 119.
Routability of a design is determined by the routing congestion of the design, and decreases with the increase of routing congestion. So it is essential to reduce routing congestion in a design before going to detailed routing. Generally routing congestion of a design is determined by the global routing at stage 111, but it can be improved at the floor planning block placement stage 109. So if a design is found to be over congested 113 at the global routing stage 111, then the design needs to be placed again. This process continues until the design comes to a satisfactory congestion level. Manual iteration 115 is possible for a small design to reach a required congestion level, but for a big and/or complex mixed-signal design it is cumbersome or near impossible to do so.
Unlike the digital domain, spaces in custom domain are very irregular. This increases the complexity in a custom block placer as it needs to search and optimize the entire design space. In custom design flow it is fairly uncommon to optimize congestion at the placement stage because of this complexity; but with the increasing size and complexity in analog/mixed-signal design, it has become essential to optimize routing congestion for custom block placers.